1. Field of the Invention
The present invention relates to a configuration of circuitry for a programmable logic device (PLD) to limit the number of product term lines need to perform a Boolean operation.
2. Background
FIG. 1 shows an array structure for a typical prior art programmable array logic (PAL) device, a type of PLD. The PAL of FIG. 1 has six inputs I.sub.0-5 and four outputs O.sub.0-3. The PAL device further has an AND array 100 followed by an OR array 102. An input such as I.sub.0 to the PAL has a true output 104 and a complement output 106 forming rows connected to programmable interconnect cells 108 containing individual cells, such as 110. A cell like cell 110 may be programmed to be connected or disconnected to an AND gate in the AND array 100. Nonprogrammable interconnect points 120 connect the output of the AND gates 100 to the OR gates of the OR array 102. Although points 120 are described as nonprogrammable, programmable cells may likewise be used. Additional programmable features may also be added, such an output macro cell 114 which is programmable to allow an output to be either registered or combinatorial.
A group of cells as shown at 112 may be connected to an AND gate with the output of the AND gate providing a product term. Although shown as an AND array 100, in reality the AND array 100 has AND gates implemented using NOR gates with true and complement row connections to cells 108 reversed internally. An example of the PLD with circuitry similar to that shown and described with respect to FIG. 1 is included in the MACH 4 PLDs manufactured by Lattice/Vantis Semiconductor Corporation of Sunnyvale, California.
FIG. 2 illustrates programming of a PAL device as shown in FIG. 1 to perform the Boolean operation /a*b+a*/b+/b+a, where "/" indicates a Boolean NOT, "*" indicates a Boolean AND, and "+" indicates a Boolean OR operation. The PAL device of FIG. 2 receives two inputs "a" and "b". Inverting/Noninverting buffers 200 provides a and its inverse /a, while inverting/noninverting buffer 202 provides b and its inverse /b to be selectively connected to form four product terms 210-213. For the first product term 210, /a and b are connected to form the Boolean equation /a*b. For the second product term 211, a and /b are connected to form the Boolean equation a*/b. For product term 212 only /b is connected, while for product term 213 only a is connected. Note that connected programmable interconnect cells are represented by a darkened circle symbol, while interconnect cells programmed to be unconnected are shown as a circle without darkening. The product terms 210-213 are provided to inputs of an OR gate 220, so the output of OR gate 220 provides the desired Boolean operation /a*b+a*/b+/b+a.